Local data networks with a plurality of microcontrollers are often provided in machines such as, for example, printers or copiers in which the individual modules of the machines are respectively controlled by one or more microcontrollers and the microcontrollers communicate with all modules over such a data network. These data networks are often based on the CAN bus. The CAN bus or the corresponding protocol is explained in detail in CAN Controller Error Network, Grundlage und Praxis, 2nd edition, 1997 (ISBN 3-7785-2575-1). A CAN bus is a serial data bus that is typically realized with a differential two-wire line. The messages are transferred in what are known as CAN telegrams or CAN frames. Such a CAN data telegram comprises a start bit, an identifier comprising 11 bits, a further seven control bits, 0-8 data bytes and further control bits that follow the data bytes. The design of a CAN data telegram can differ depending on the specification; there is thus a CAN specification 2.0A and a CAN specification 2.0B. The arbitration is executed per bit and without control. This means that the transmitter that prevails (based on its priority) in the data bus relative to other transmitters does not have to resend its telegram. The control bits provides by the data bytes are used for arbitration, whereby the arbitration essentially occurs via the bits of the identifier.
A further development of the CAN bus is designated as a PeliCAN that is equipped with further service features relative to the conventional CAN bus. A stand-alone CAN controller with the designation SJA 1000, which completely supports the CAN 2.0B protocol and additionally can be operated in the PeliCAN mode, is offered by the firm Philips. This controller is described in detail in the datasheet of 4 Jan. 2000.
A machine controlled by a plurality of processors emerges from U.S. Pat. No. 4,737,907, whereby one of the processors is a master processor and the further processors are activated by the master processor in order to execute specific actions. Clock signals that are supplied to all processors are generated by means of a breaker plate. The master processor can therefore send a command to a further processor and combine this command with a delay time, such that these further microcontrollers only execute the command after the expiration of the delay time. The delay time is specified in a specific number of clock pulses. Via the use of the clock pulses, the master processor does not always have to output to the further microcontrollers its respective commands for execution of the actions at the point in time at which the commands should be executed, but rather can send out the respective commands early and tend to other actions after sending the commands. The master processor is thus unloaded.
If the communication between the master processor and the further processors were to be executed over a data network in which the delays for transfer of messages can vary and in particular depend on the load of the data network, the individual actions cannot be executed at an exact predetermined point in time, since this point in time would be affected by the transfer time of the individual messages.
A hardware circuit in which various processing components can communicate with one another is shown in U.S. Pat. No. 3,614,745.
A local network for the control of a plurality of processors and control cards at a printing machine emerges from DE 100 59 270 A1. The individual processes on the control cards are synchronized with the aid of a centrally-generated system tract that is transferred to the individual control cards over a free line. The individual actions are initiated by the control cards, dependent on an angle setting of the machine, whereby a specific angle setting, the rotation speed, and the acceleration at a specific point in time from which other angle settings are then extrapolated, are transferred to the control cards.
A multiprocessor system in which a plurality of autonomous processes use the same address range of a storage emerges from U.S. Pat. No. 5,313,620.
DE 198 22 146 A1 specifies a device for communication between a plurality of electrical components such as, for example, sensors, actuators or gauges. This device comprises a master and a number of slaves, corresponding to the number of the electrical components that are connected with one another via a bidirectional interface. The master generates the synchronization pulses, clock signals and transmission pulses, whereby a synchronization pulse respectively initiates a cycle in which a specific number of clock signals are switched on the bidirectional interface.
A method with which two processors can access a common storage device that is a dual-ported RAM, whereby no arbitration logic is necessary, emerges from DE 199 20 992 A1. For this, an item of information stored in the dual-ported RAM is read out n times and subsequently compared. If the n determined items of information are identical, the read information is correct. Otherwise the read event must be repeated.
A routing device for coupling of various telecommunication networks with different protocols and different transfer properties emerges from DE 199 28 930 A1. With this device, narrow-band military special networks should in particular be coupled to broadband civil networks and/or other narrow-band military special networks. Routers allow networks with different network protocols to connect. Using the address of a data packet, routers determine which router or which workstation should receive the packet next. Based on a routing table, routers ensure that the packets reach their goal in the most efficient way possible. When a connection between two routers is disturbed, the transmitting router can determine an alternative path in order to sustain the traffic flow.